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complete, 12-bit, 45 mhz ccd signal processor ADDI7100 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2010 analog devices, inc. all rights reserved. features pin-compatible upgrade for the ad9945 45 mhz correlated double sampler (cds) with variable gain 6 db to 42 db, 10-bit variable gain amplifier (vga) low noise optical black clamp circuit preblanking function 12-bit, 45 mhz adc no missing codes guaranteed 3-wire serial digital interface 3 v single-supply operation space-saving, 32-lead, 5 mm 5 mm lfcsp applications digital still cameras digital video camcorders pc cameras portable ccd imaging devices cctv cameras general description the ADDI7100 is a complete analog signal processor for charge- coupled device (ccd) applications. it features a 45 mhz, single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area ccd arrays. the signal chain for the ADDI7100 consists of a correlated double sampler (cds), a digitally controlled variable gain amplifier (vga), a black level clamp, and a 12-bit adc. the internal registers are programmed through a 3-wire serial digital interface. programmable features include gain adjustment, black level adjustment, input clock polarity, and power-down modes. the ADDI7100 operates from a single 3 v power supply, typically dissipates 125 mw, and is packaged in a space-saving, 32-lead lfcsp. functional block diagram dataclk shd shp band gap reference dout d0 to d11 ccdin pbl k reft refb internal timing 6db to 42db ? 3db, 0db, +3db, +6db avdd dvdd dvss avss drvdd drvss 10 digital interface sdata sck sl clpob 12 cds vga clp ADDI7100 control registers 12-bit adc vd 07608-001 figure 1.
ADDI7100 rev. c | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 general specifications ................................................................. 3 digital specifications ................................................................... 3 system specifications ................................................................... 4 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 equivalent input circuits .............................................................. 10 terminology .................................................................................... 11 circuit description and operation .............................................. 12 dc restore .................................................................................. 12 correlated double sampler (cds) .......................................... 12 optical black clamp .................................................................. 12 analog-to-digital converter (adc) ....................................... 13 variable gain amplifier (vga) ............................................... 13 digital data outputs .................................................................. 13 applications information .............................................................. 14 initial power-on sequence ....................................................... 15 grounding and decoupling recommendations .................... 15 serial interface timing .................................................................. 16 complete register listing ............................................................. 17 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 6/10rev. b to rev. c changes to 0x0d description and 0xff description in table 8 .............................................................................................. 18 9/09rev. a. to rev. b changes to features section............................................................ 1 changed power-down mode to full standby mode, table 1 .... 3 moved timing diagrams section .................................................. 5 changes to table 4, figure 3, and figure 4 ................................... 5 changes to figure 9 caption ......................................................... 10 changes to optical black clamp section .................................... 12 changes to initial power-on sequence section ......................... 15 changes to figure 16 ...................................................................... 16 changes to table 8 .......................................................................... 17 2/09rev. 0 to rev. a changes to serial interface timing section ................................ 16 changes to figure 16 and figure 17 ............................................. 16 10/08revision 0: initial version
ADDI7100 rev. c | page 3 of 20 specifications general specifications t min to t max , avdd = dvdd = drvdd = 3 v, f samp = 45 mhz, unless otherwise noted. table 1. parameter min typ max unit temperature range operating ?25 +85 c storage ?65 +150 c power supply voltage analog, digital, digital driver 2.7 3.6 v power consumption normal operation 125 mw full standby mode 1 mw maximum clock rate 45 mhz digital specifications drvdd = dvdd = 2.7 v, c l = 20 pf, unless otherwise noted. table 2. parameter symbol min typ max unit logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs high level output voltage, i oh = 2 ma v oh 2.2 v low level output voltage, i ol = 2 ma v ol 0.5 v
ADDI7100 rev. c | page 4 of 20 system specifications t min to t max , avdd = dvdd = drvdd = 3 v, f samp = 45 mhz, unless otherwise noted. table 3. parameter test conditions/comments min typ max unit cds input characteristics definition 1 allowable ccd reset transient 0.5 1.2 v cds gain accuracy vga gain = 6 db (code 15, default value) ?3 db cds gain ?2.45 ?2.95 ?3.45 db 0 db cds gain default setting 5.40 5.90 6.40 db +3 db cds gain 8.65 9.15 9.65 db +6 db cds gain 11.10 11.60 12.10 db maximum input range before saturation 0 db cds gain default setting 1.0 v p-p ?3 db cds gain 1.4 v p-p +6 db cds gain 0.5 v p-p maximum ccd black pixel amplitude positive offset definition 1 0 db cds gain default setting ?100 +200 mv +6 db cds gain ?50 +100 mv variable gain amplifier (vga) gain control resolution 1024 steps gain monotonicity guaranteed gain range minimum gain (vga code 15) see figure 13 for vga curve 6.0 db maximum gain (vga code 1023) see variable gain amplifier (vga) section for vga gain equation 42.0 db black level clamp measured at adc output clamp level resolution 2048 steps clamp level measured at adc output minimum clamp level (code 0) 0 lsb maximum clamp level (code 1023) 511 lsb adc resolution 12 bits differential nonlinearity (dnl) ?1.0 0.5 lsb no missing codes guaranteed full-scale input voltage 2.0 v voltage reference reference top voltage (reft) 2.0 v reference bottom voltage (refb) 1.0 v system performance specifications include entire signal chain gain accuracy low gain (vga code 15) 6 db total ga in (default cds, vga) 5.4 5.9 6.4 db maximum gain (vga code 1023) 41.4 41.9 42.4 db peak nonlinearity, 1 v input signal 6 db total gain (default cds, vga) 0.1 % total output noise ac grounded input, 6 db total gain 0.8 lsb rms power supply rejection (psr) measured wi th step change on supply 45 db 1 input signal characteristics are defined as shown in . figure 2 100mv typ optical black pixel 500mv typ reset transient 1v typ input signal range 0 7608-002 figure 2.
ADDI7100 rev. c | page 5 of 20 timing specifications c l = 20 pf, f samp = 45 mhz, unless otherwise noted. see figure 3 , figure 4 , and figure 16 . table 4. parameter symbol min typ max unit sample clocks dataclk, shp, shd clock period t conv 22 ns dataclk high/low pulse width t adc 9 11 ns shp pulse width t shp 5.5 ns shd pulse width t shd 5.5 ns clpob pulse width 1 2 20 pixels shp rising edge to shd falling edge t s3 5.5 ns shp rising edge to shd rising edge t s1 9 11 t conv ? t s2 ns shd rising edge to shp rising edge t s2 9 11 t conv ? t s1 ns shd rising edge to shp falling edge t s4 5.5 ns internal clock delay t id 4 ns d a t a o u t p u t s output delay t od 15 ns pipeline delay 15 cycles serial interface maximum sck frequency (must not exceed pixel rate) f sclk 40 mhz sl to sck setup time t ls 10 ns sck to sl hold time t lh 10 ns sdata valid to sck rising edge setup t ds 10 ns sck rising edge to sdata valid hold t dh 10 ns 1 minimum clpob pulse width is for functional operation only. wi der typical pulses are recommended to achieve low noise clamp pe rformance. timing diagrams pixel n pixel n + 1 pixel n + 2 pixel n + 14 pixel n + 15 t od t s3 t s4 t id t id n ? 15 n ? 14 n ? 13 n ? 1 n notes 1. recommended placement for dataclk rising (active) edge is near the shp or shd risin g (active) edge. the best location for lowest noise will be system dependent. 2 . ccd signal is sampled at shp and shd rising edges. shp shd dataclk output data ccd signal (ccdin) t s1 t conv t s2 07608-012 figure 3. ccd sampling timing (default polarity settings)
ADDI7100 rev. c | page 6 of 20 07608-013 ccd signal (ccdin) effective pixels clpob optical black pixels horizont a l blanking dummy pixels effective pixels pblk notes 1. clpob and pblk should be aligned with the ccd signal input (ccdin). clpob wi l l overwrite pblk. pblk will not affect clamp operation if overlapping with clpob. 2 . pblk sign a l is optional. keep the pblk pin in the inactive state if not used. 3 . digital output data will be all zeros during pblk. output data latency is fifteen dataclk cycles. o utput data effective pixel data ob pixel data dummy black effective data active active figure 4. typical clamp timing (default polarity settings)
ADDI7100 rev. c | page 7 of 20 absolute maximum ratings thermal resistance table 5. parameter rating avdd to avss ?0.3 v to +3.9 v dvdd to dvss ?0.3 v to +3.9 v drvdd to drvss ?0.3 v to +3.9 v digital outputs to drvss ?0.3 v to drvdd + 0.3 v shp, shd, dataclk to dvss ?0.3 v to dvdd + 0.3 v clpob, pblk to dvss ?0.3 v to dvdd + 0.3 v sck, sl, sdata to dvss ?0.3 v to dvdd + 0.3 v reft, refb, ccdin to avss ?0.3 v to avdd + 0.3 v junction temperature 150c lead temperature (10 sec) 300c ja is specified for a device with the exposed bottom pad soldered to the circuit board ground. table 6. thermal resistance package type ja unit 32-lead lfcsp 27.7 c/w esd caution stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ADDI7100 rev. c | page 8 of 20 pin configuration and fu nction descriptions pin 1 indicator 24 refb 23 reft 22 ccdin 21 avss d2 1 d3 2 d4 3 32 d1 20 avdd 19 shd 18 shp 17 clpob d10 9 d11 10 drvdd 11 drvss 12 dvdd 13 dataclk 14 dvss 15 pblk 16 d5 4 d6 5 d7 6 d8 7 d9 8 31 d0 30 nc 29 nc 28 vd 27 sck 26 sdata 25 sl notes 1. it is recommended that the exposed pad be soldered to the ground plane of the pcb. 2. nc = no connect. 07608-003 ADDI7100 top view (not to scale) figure 5. pin configuration table 7. pin function descriptions pin no. mnemonic type 1 description 1 to 10 d2 to d11 do digital data outputs. 11 drvdd p digital output driver supply. 12 drvss p digital output driver ground. 13 dvdd p digital supply. 14 dataclk di digital data output latch clock. 15 dvss p digital supply ground. 16 pblk di preblanking clock input. 17 clpob di black level clamp clock input. 18 shp di cds sampling clock for ccd reference level. 19 shd di cds sampling clock for ccd data level. 20 avdd p analog supply. 21 avss p analog ground. 22 ccdin ai analog input for ccd signal. 23 reft ao adc top reference voltage decoupling. 24 refb ao adc bottom reference voltage decoupling. 25 sl di serial digital interface load pulse. 26 sdata di serial digital interface data input. 27 sck di serial digital interface clock input. 28 vd di vertical sync input. controls the update time of vd-updated registers. if this pin is not needed, it should be tied to gnd. 29, 30 nc nc not internally connected. 31, 32 d0, d1 do digital data output. 1 ai = analog input, ao = analog output, di = digital input, do = digital output, p = power, and nc = no connect.
ADDI7100 rev. c | page 9 of 20 typical performance characteristics 0 20 40 60 80 100 120 140 160 180 200 10 22 36 45 3.6v 3.0v 2.7v 07608-018 sample rate (mhz) power (mw) figure 6. power vs. sample rate 07608-016 code dnl (lsb) ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 270 808 1346 1884 2422 2960 3498 4036 1 539 1077 1615 2153 2691 3229 3767 figure 7. typical dnl performance ?5 ?4 ?3 ?2 ?1 0 1 2 3 07608-017 code inl (lsb) 1 262 523 784 1045 1306 1567 1828 2089 2350 2611 2872 3133 3394 3655 3916 figure 8. typical inl performance
ADDI7100 rev. c | page 10 of 20 equivalent input circuits dvdd dvss 330 ? input 07608-004 figure 9. digital inputs shp, shd, dataclk, clpob, pblk, sck, sl, sdata, and vd dr v dd drvss three- state data d[0:11] dvss dvdd 07608-005 figure 10. data outputs a v dd avss 60 ? avss 07608-006 figure 11. ccdin (pin 22)
ADDI7100 rev. c | page 11 of 20 terminology differential nonlinearity (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. therefore, every code must have a finite width. no missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions. peak nonlinearity peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the ADDI7100 from a true straight line. the point used as zero scale occurs 0.5 lsb before the first code transition. positive full scale is defined as a level that is 1.5 lsb beyond the last code transition. the deviation is measured from the middle of each particular output code to the true straight line. the error is then expressed as a percentage of the 2 v adc full-scale signal. the input signal is always gained appropriately to fill the full-scale range of the adc. tot a l o utput noi s e the rms output noise is measured using histogram techniques. the standard deviation of the adc output codes is calculated in lsbs and represents the rms noise level of the total signal chain at the specified gain setting. the output noise can be converted to an equivalent voltage, using the relationship 1 lsb = ( adc full scale /2 n codes) where n is the bit resolution of the adc. for example, 1 lsb of the ADDI7100 is 0.5 mv. power supply rejection (psr) psr is measured with a step change applied to the supply pins. this represents a very high frequency disturbance on the power supply of the ADDI7100. the psr specification is calculated from the change in the data outputs for a given step change in the supply voltage. internal delay for shp/shd the internal delay (also called aperture delay) is the time delay that occurs from the time a sampling edge is applied to the ADDI7100 until the actual sample of the input signal is held. both shp and shd sample the input signal during the transi- tion from low to high; therefore, the internal delay is measured from the rising edge of each clock to the instant that the actual internal sample is taken.
ADDI7100 rev. c | page 12 of 20 circuit description and operation 0.1f 07608-010 6db to 42db ccdin clpob dc restore optical black clamp 12-bit adc dac 11 10 internal v ref 2v full scale 12 clpob pblk dataclk data output latch shp shd pblk dcbyp shp ?3db, 0db, +3db, +6db vga cds vga gain register digital filtering clamp level register blank to zero or clamp level dout d0 to d11 figure 12. ccd mode block diagram the ADDI7100 signal processing chain is shown in figure 12 . each processing step is essential for achieving a high quality image from the raw ccd pixel data. dc restore to reduce the large dc offset of the ccd output signal, a dc restore circuit is used with an external 0.1 f series coupling capacitor. this circuit restores the dc level of the ccd signal to approximately 1.5 v, which is compatible with the 3 v supply of the ADDI7100. correlated double sampler (cds) the cds circuit samples each ccd pixel twice to extract video information and to reject low frequency noise. the timing shown in figure 3 illustrates how the two cds clocks, shp and shd, are used to sample the reference level and the data level, respectively, of the ccd signal. the ccd signal is sampled on the rising edges of shp and shd. placement of these two clock signals is critical for achieving the best performance from the ccd. an internal shp/shd delay (t id ) of 4 ns is caused by internal propagation delays. optical black clamp the optical black clamp loop removes residual offsets in the signal chain and tracks low frequency variations in the ccd black level. during the optical black (shielded) pixel interval on each line, the adc output is compared with the fixed black level reference selected by the user in the clamp level register (address 0x04). the resulting error signal is filtered to reduce noise, and the correction value is applied to the adc input through a dac. normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. if external digital clamping is used during postprocessing, optical black clamping for the ADDI7100 can be disabled using address 0x00, bit 2. when the optical black clamp loop is disabled, the clamp level register can still be used to provide programmable offset adjustment. note that if the clpob is disabled, higher vga gain settings reduce the dynamic range because the uncorrected offset in the signal path is amplified. horizontal timing is shown in figure 4 . align the clpob pulse with the optical black pixels of the ccd. it is recommended that the clpob pulse be used during valid ccd dark pixels. it is recommended that the clpob pulse should be 20 pixels wide to minimize clamp noise. shorter pulse widths can be used, but the ability of the loop to track low frequency variations in the black level is reduced.
ADDI7100 rev. c | page 13 of 20 analog-to-digital converter (adc) the ADDI7100 uses a high performance adc architecture optimized for high speed and low power. differential non- linearity (dnl) performance is typically better than 0.5 lsb. the adc uses a 2 v full-scale input range. variable gain amplifier (vga) the vga stage provides a gain range of 6 db to 42 db, pro- grammable with 10-bit resolution through the serial digital interface. the minimum gain of 6 db is needed to match a 1 v input signal with the adc full-scale range of 2 v. a plot of the vga gain curve is shown in figure 13 . vga gain (db) = ( vga code 0.0358 db) + 5.4 db where code is in the range of 0 to 1023. vga gain register mode 42 12 383 127 v g a gain (db) 0 30 255 36 24 18 6 511 639 767 895 1023 0 7608-011 figure 13. vga gain curve digital data outputs by default, the digital output data is latched by the rising edge of the dataclk input. output data timing is shown in figure 3 . it is also possible to make the output data latch transparent, immediately validating the data outputs from the adc. setting the doutlatch register (address 0x01[5]) to 1 configures the latch as transparent. the data outputs can also be disabled by setting the dout_off register (address 0x01[4]) to 1.
ADDI7100 rev. c | page 14 of 20 applications information the ADDI7100 is a complete analog front-end (afe) product for digital still camera and camcorder applications. as shown in figure 14 , the ccd image (pixel) data is buffered and sent to the ADDI7100 analog input through a series input capacitor. the ADDI7100 performs the dc restoration, cds sampling, gain adjustment, black level correction, and analog-to-digital conversion. the digital output data of the ADDI7100 is then processed by the image processing asic. the internal registers of the ADDI7100used to control gain, offset level, and other functionsare programmed by the asic or by a microprocessor through a 3-wire serial digital interface. a system timing generator provides the clock signals for both the ccd and the afe (see figure 14 ). 0.1 f 07608-014 ccd ccdin buffer v out ADDI7100 adc out register data serial interface digital outputs digital image processing asic timing generator v-driver ccd timing cds/clamp timing figure 14. system applications diagram 24 refb 23 reft 22 ccdin 21 avss d2 1 d3 2 d0 d1 d4 3 20 avdd 19 shd 18 shp 17 clpob d5 4 d6 5 d7 6 d8 7 d9 8 data outputs 12 d10 d11 910 3v driver supply 3v analog supply 3v analog supply drvdd drvss dvdd dvss pblk 12 13 14 15 16 5 clock inputs 3 serial interface ccdin ADDI7100 top view (not to scale) 1.0f 1.0f 0.1f 0.1f 0.1f 0.1f nc = no connect (not internally connected, may be tied to ground or left floating). pin 1 identifier 32 31 30 29 28 27 26 25 nc nc vd sck sdata sl 11 dataclk 07608-015 vd output from asic/dsp (should be grounded if not used.) figure 15. recommended circui t configuration for ccd mode
ADDI7100 rev. c | page 15 of 20 initial power-on sequence after power-on, the ADDI7100 automatically resets all internal registers to default values. settling of the internal voltage refer- ence takes approximately 1 ms to complete. during this time, normal clock signals and serial write operations can take place, but valid output data do not occur until the reference is fully settled. when loading the desired register settings, the startup register (address 0x05[1:0]) must be set to 0x3. grounding and decoupling recommendations as shown in figure 15 , a single ground plane is recommended for the ADDI7100. this ground plane should be as continuous as possible to ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. place all decoupling capacitors as close as possible to the package pins. a single clean power supply is recommended for the ADDI7100, but a separate digital driver supply can be used for drvdd (pin 11). always decouple drvdd to drvss (pin 12), which should be connected to the analog ground plane. the advantages of using a separate digital driver supply include using a lower voltage (2.7 v) to match levels with a 2.7 v asic, and reducing digital power dissipation and potential noise coupling. if the digital outputs must drive a load larger than 20 pf, buffering is the recommended method to reduce digital code transition noise. alternatively, placing series resistors close to the digital output pins may also help to reduce noise. note that the exposed pad on the bottom of the package should be soldered to the ground plane of the printed circuit board.
ADDI7100 rev. c | page 16 of 20 serial interface timing all ADDI7100 internal registers are accessed through a 3-wire serial interface. each register consists of an 8-bit address and a 16-bit data-word. both the address and the data-word are written starting with the lsb. to write to each register, a 24-bit operation is required, as shown in figure 16 . although many data-words are fewer than 16 bits wide, all 16 bits must be written for each register. for example, if the data-word is only eight bits wide, the upper eight bits are dont care bits and must be filled with zeros during the serial write operation. if fewer than 16 data bits are written, the register is not updated with new data. figure 17 shows a more efficient way to write to the registers, using the ADDI7100 address autoincrement capability. using this method, the lowest desired address is written first, followed by multiple 16-bit data-words. each data-word is automatically written to the address of the next highest register. by eliminating the need to write each address, faster register loading is achieved. continuous write operations can start with any register location. 07608-019 a2 sdata a0 a1 a4 a5 a6 a7 d0 d1 d2 d3 d13 d14 d15 sl a3 t ls 8-bit address 16-bit dat a 24 4 5 6 7 8 9 10 11 12 22 23 t lh t dh t ds notes 1. sdata bits are latched on sck rising edges. sck can idle high or low between write operations. 2. all 24 bits must be written: 8 bits for address and 16 bits for data. 3. if the register length is less than 16 bits, then zeros must be used to complete the 16-bit data length. 4. new data values are updated in the specified register location at different times, depending on the particular register written to. sck 123 figure 16. serial write operation notes 1. multiple sequential registers can be loaded continuously. 2. the first (lowest address) register address is written, followed by multiple 16-bit data-words. 3. the address automatically increments with each 16-bit data-word (all 16 bits must be written). 4. sl is held low until the last desired register has been loaded. 07608-020 sdata a0 a1 a2 a6 a7 d0 d1 d14 d15 sck sl a3 d0 d1 d14 d15 d0 data for starting register address data for next register address d2d1 1 24 234 78910 23 2625 40 39 42 41 43 figure 17. continuous serial write operation
ADDI7100 rev. c | page 17 of 20 complete register listing note that when an address contains fewer than 16 data bits, all remaining bits must be written as zeros. table 8. afe address data bits default value update type 1 name description 0x00 [1:0] 0 sck standby 00: normal operation 01: reference standby 10: full standby 11: full standby [2] 0x1 clamp_en 1: enable black clamp 0: disable black clamp [3] 0 fastclamp 0: normal clpob settling 1: faster clpob settling [4] 0 fastupdate 1: enable very fast clamping when cds gain is changed 0: ignore cds gain updates [5] 0 pblk_lvl 0: blank to 0 1: blank to clamp level [6] 0 dcbyp 0: normal dc restore operation 1: dc restore disabled during pblk active [8:7] 0x2 test test use only; must be set to 2 [10:9] 0x2 test test use only; must be set to 2 0x01 [0] 0 sck shpd_pol 0: rising edge sample 1: falling edge sample [1] 0 dataclk_pol 0: rising edge triggered 1: falling edge triggered [2] 0 clp_pol 0: active low 1: active high [3] 0 pblk_pol 0: active low 1: active high [4] 0 dout_off 0: data outputs are driven 1: data outputs are disabled (high-z) [5] 0 doutlatch 0: retime data outputs with output latch (using dataclk) 1: do not retime data outputs; output latch is transparent [6] 0 gray_en 1: gray encode adc outputs 0x02 [2:0] 0x1 sck/vd cdsgain cds gain setting: 0x0: ?3 db 0x1: 0 db 0x2: +3 db 0x3: +6 db 0x03 [9:0] 0x0f sck/vd vgagain vga gain , 6 db to 42 db (0.0358 db per step) 0x04 [10:0] 0x1ec sck/vd clamplevel optical black clamp level, 0 lsb to 511 lsb (0.25 lsb per step) 0x05 [1:0] 0 sck startup must be set to 0x3 after power-up [3:2] 0 test test use only; must be set to 0 0x06 [2:0] 0x6 sck test test use only; must be set to 6 [3] 0 test test use only; must be set to 0 [5:4] 0 test test use only; must be set to 0 0x07 [0] 0 sck test test use only; must be set to 0 0x08 [11:0] 0xfff sck test test use only; must be set to 0xfff 0x09 [11:0] 0xfff sck test test use only; must be set to 0xfff 0x0a [0] 0 sck test test use only; must be set to 0 0x0b [0] 0 sck sw_rst 1: software reset; au tomatically resets to 0 after software reset 0x0c [0] 0x1 sck outcontrol data output control: 0: make all outputs dc inactive 1: enable data outputs
ADDI7100 rev. c | page 18 of 20 address data bits default value update type 1 name description 0x0d [0] 0 sck vd_pol 0: falling edge triggered 1: rising edge triggered 0x0e [6:0] 0 sck reg_update set the appropriate bits hi gh to enable vd update of the selected registers: [0]: cdsgain (register 0x02) [1]: vgagain (register 0x03) [2]: clamplevel (register 0x04) [3]: test use only; must be set to 0 [4]: test use only; must be set to 0 [5]: test use only; must be set to 0 [6]: test use only; must be set to 0 0xff [0] 0 sck test test use only; do not access 1 sck = register is immediately updated when the 16th data bit (d15) is written. vd = register is updated at the vd falling edge .
ADDI7100 rev. c | page 19 of 20 outline dimensions compliant to jedec standards mo-220-vhhd-2 011708-a 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indi c ator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 18. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADDI7100bcpz ?25c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-2 ADDI7100bcpzrl ?25c to +85c 32-l ead lead frame chip scale package [lfcsp_vq] cp-32-2 1 z = rohs compliant part.
ADDI7100 rev. c | page 20 of 20 notes ?2008C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07608-0-6/10(c)

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